The use of programmable delay lines in integrated circuits for signal de-skewing is well-known. For example, FIG. 1 illustrates a conventional approach to reducing signal skew by forming a differential delay line which incorporates a differential delay element 100 having reduced duty cycle distortion. As apparent from the figure, this approach employs two inverter chains, a first inverter chain including a first inverter 102, and a second inverter chain including a second inverter 104. An input signal, IP, to the first inverter 102 may be a complementary clock signal while a second input signal, IN, to the second inverter 104 may be a normal (e.g., true) clock signal. The differential delay element 100 further includes a pair of cross-coupled inverters, 106 and 108, connected between the first and second inverter chains. An output of inverter 108 is connected to an output of the first inverter 102, and input of inverter 108 is connected to an output of the second inverter 104, an output of inverter 106 is connected to the output of the second inverter 104, and an input of inverter 106 is connected to the output of the first inverter 102.
The cross-coupled inverters 106 and 108, which are low-strength (weak) inverters, ensure that the rise and fall times of the two inverter chains are balanced. This tends to equalize the propagation delay for rising and falling edges. A more detailed description of this approach can be found in an article by N. Tiwari and R. Saraswat, entitled “Skew generation and analysis in timing-critical circuits,” EDN, pp. 87-96, Nov. 13, 2003, the disclosure of which is incorporated by reference herein. Duty cycle distortion due to different propagation delay times for rising and falling edges can introduce duty cycle distortion in variable delay lines. This duty cycle distortion can be a function of the selected delay value. This is true even when the delay line is constructed from inherently duty cycle distortion resistant delay elements such as described in conjunction with FIG. 1.
Accordingly, there exists a need for techniques for reducing duty cycle distortion in a delay circuit which do not suffer from one or more of the above-described problems associated with conventional delay circuitry.